Digital signal processing system for limiting a result to be predetermined bit count

ABSTRACT

A video codec (coder-decoder) system inputs consecutively admitted frames of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each block of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.

This is a continuation of application Ser. No. 07/807,510, filed Dec. 16, 1991, now abandoned, which is a continuation of application Ser. No. 07/483,840, filed Feb. 23, 1990, now U.S. Pat. No. 5,130,797.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital signal processing system and, more particularly, to a video codec system which turns input video data into divisions thereof, the divisions being coded in parallel and composed again for transmission to a receiving side.

2. Description of the Prior Art

FIG. 1 is a block diagram of a video coder implementing a typical prior art video codec method illustratively shown in "A Real-time Video Signal Processor Suitable for Motion Picture Coding Applications" (IEEE GLOBECOM '87, pp. 453-457, 1987). In this figure, reference numeral 1 is input video data; 2 is a plurality of digital signal processors (DSP's) which are disposed in parallel and which code the input video signal in parallel; 3 is a pair of data transfer controllers for controlling the division of the data and the transfer thereof to the DSP's 2; 4 is the data to be transferred from the data transfer controllers 3 to each of the DSP's 2; and 5 is the data processed by the DSP's 2.

In operation, the data transfer controllers 3 turn a single frame of the input video data 1 into divisions and distribute them to the DSP's 2. After being processed by the DSP's, the transferred data 4 is forwarded as the processed data 5 to the next processing block. FIG. 2(a) shows the data area to be processed by each of the DSP's 2. As indicated, the input video data 1 is turned in this case into four divisions, A through D, for parallel processing by the DSP's 2. All DSP's equally share the burden of the processing. The four areas constitute the single frame of the input video data 1 that was divided earlier.

A case may be assumed in which the input video data 1 is coded by a prior art interframe video coding method or its equivalent. This method generally involves conditional pixel compensation processing. That is, what is coded by this method is only those portions of video data whose differential between a given input frame and its preceding frame exceeds a certain level of magnitude; the remaining data portions are replaced by the previous frame data when coded. There may thus occur a case where the number of pixels is the same for the areas to be covered by the DSP's 2 but the amount of operation needed to perform the processing is not the same for these areas. In that case, the amount of operational requirements or the required operation time is proportional to the rate of effective pixels.

FIG. 2(b) is an example of how effective pixels are distributed where the input video data 1 is turned into four divisions, A through D, by the interframe coding method. The time required for the DSP's 2 to operate on each block of data is equivalent to the time taken by the DSP 2 whose number of effective pixels is the largest.

Where the numbers of effective pixels are unevenly distributed or vary over time throughout single frame input video data, the prior art video codec method, structured as outlined above, has been dependent for its processing time on the performance of the DPS whose processing time is the longest. A disadvantage of this scheme is that the overall processing efficiency per frame tends to be reduced. Another disadvantage is that where coding extends across different processing areas, the coordination of processes between the DPSs becomes complicated.

FIGS. 3 through 5 are views explaining how a typical prior art motion compensation method works, an example thereof being found illustratively in "Interframe Coding Using Motion Compensation and Predictive Coding" (Hideo Kuroda, Naoki Takekawa, Hideo Hashimoto; 85/1 Vol. J68-B No. 1, pp. 77-84; periodical of the Japan Society of Telecommunications Researchers). This example describes in particular a way to carry out a total search algorithm.

In FIGS. 3 through 5, reference numeral 21 is an input signal that conveys input video data; 22 is an input frame buffer that temporarily stores a single frame of input data; and 23 is a current input block with a block size of l1×l2 for motion compensation at a given location in the current input frame. Reference numeral 24 is a motion vector search range delimited by the limits l1+2m, l2+2n within which exists a block to be matched with the current input block 23 in preceding input frame reproduction data. In this case, the number of blocks (M blocks) to be searched for is given as

    M=(2m+1)×(2n+1)                                      (100)

Thus the search range is between -m and +m pixels horizontally, and between -n and +n pixels vertically.

Motion compensation works as follows: In an interframe codec system, a frame-to-frame correlation is found between the current input frame data and the preceding input frame reproduction data. By use of this correlation, a process is performed in units of blocks to obtain the predictive signal closest to the current input frame data.

The motion vector search range 24 in the preceding input frame reproduction data is searched for the block whose block-to-block distortion is the smallest relative to the current input block, i.e., whose correlation thereto is the highest. A typical condition for this case to work is that the sum of absolute differential values be the smallest. This process provides motion vector and predictive signal data.

Also in FIGS. 3 through 5, reference numeral 25 is a motion compensation circuit that obtains a predictive signal by making correlation approximations on the current input block 23 of the input signal 21 and on the motion vector search range 24 given as the preceding input signal reproduction data; 26 is a predictive signal output by the motion compensation circuit 25; 27 is motion vector information that is also output by the motion compensation circuit 25.

Reference numeral 29 is a coder that outputs a coded signal 30 by coding a differential signal 28 derived from the difference between the input block signal 23 and the predictive signal 26; 31 is decoder that decodes the coded signal 30 following the coding by the coder 29.

Reference numeral 34 is a frame memory which adds the decoded signal 32 from the decoder 31 and the predictive signal 26 from the motion compensation circuit 25 to generate reproduction data 33 for storage, thereby providing the motion compensation circuit 25 with the vector search range 24. Numeral 35 is a transmission buffer, and 36 is a transmission signal.

Referring now to FIGS. 4 and 5, the operations involved will be further described. A block X is assumed as the current input block 23 located in a specific position inside the current input frame and measuring 1×2. With respect to the block X, there is calculated the amount of distortion among M blocks inside the motion vector search range 24 in the preceding input frame reproduction data. The calculation yields the block having the least distortion. This is the least distortion block "yi" whose position relative to the current input block 23 is obtained as a motion vector V. At the same time, a signal "ymin" corresponding to the block "yi" is output as the predictive signal 26.

The interframe codec system is also capable of generating the predictive signal 26 on the signal receiving side. For example, there may be assumed M motion vectors V to be searched for in a given motion vector search range 24, M being an integer larger than 1. In this case, the amount of distortion between the preceding frame block located in the motion vector V and the current input block is represented by the sum of absolute differential values therebetween. The distortion "di" is given as ##EQU1## The input block is given as

    X={x1, x2, . . . xL}

The block to be searched for is given as

    yi={yi1, yi2, . . . yiL}

where, i=1˜M, and L is equivalent to l1×l2. The motion vector V is given as

    V=Vi {min di|i=1˜M}                         (102)

In the case above, the amount of operation, illustratively represented by S1, is obtained using the following expression in which "a" stands for a number of machine cycles needed to add absolute differential values and "b" for a number of machine cycles to carry out a compare operation:

    S1=M(L×a+b)                                          (103)

An example may be assumed where a=1 machine cycle; b=2 machine cycles; 1=8; 2=8; m=8; and n=8. In that case, L=64 and M=289. As a result, one gets:

    S1≈19000                                           (104)

The volume of operation S1, which thus amounts to 19,000 machines cycles, is a very large value considering the hardware configuration involved. The requirement has been met by use of high-speed operation systems featuring pipeline processing or the like in keeping with the cycles of the frames making up the video signal.

How to simplify the hardware configuration has been a big challenge. Japanese Patent Laid-open No. 63-181585, "TV Signal Motion Compensation Interframe Coding Apparatus," proposes a method for compensating tree-search motions in order to reduce the amount of operation involved.

As shown in FIG. 1, the prior art tree search motion compensation method involves disposing first target blocks to be searched for (O) spaced equally apart at a low concentration inside the motion vector search range 24. When the block having the least distortion is detected from among the first target blocks, second target blocks (□) are disposed within a narrowed range around the least distortion block (O). When the block having the least distortion is again detected from among the second target blocks, third target blocks (Δ) are disposed within a further narrowed range around the least distortion block (□). Search for and detection of the least-detection blocks thus continue, until the block having the least distortion within the motion vector search range 24, in this case block (Δ), is identified.

In the case above, the amount of operation S2 is given as

    S2={9×L×a+9×b}×3                   (105)

Under the same condition as given earlier, one gets:

    S2≈1800

The operation represented by 1800 machine cycles available with the tree search motion compensation method is an appreciable reduction from the high operational requirement in the case of the total search method.

Since the prior art motion compensation method is constructed as outlined above, attempts to perform the total search, which is highly reliable, during motion compensation have inevitably led to vastly increased amounts of operation. This has required setting up hardware on large scales. Likewise, attempts to reduce the amount of operation by use of the tree search method or the like have resulted in the deterioration in the system's ability to detect the least distortion block. That is, there is a growing possibility that a block located away from the true least distortion block will be selected during matching operation of the initial low concentration block search. Where that scheme is employed, there have been increasing numbers of cases in which the system fails to detect the predetermined least distortion and incorrectly passes a judgment of no correlation between blocks. There has been little choice but to accept the resulting inefficiency in data transmission.

FIG. 8 is a block diagram illustratively showing a typical prior art video coding system, "Real-time Video Signal Processor Module" (in Proc. ICSSP '87, Apr. 1987, pp. 1961-1964). In FIG. 8, reference numeral 51 is an input terminal through which input data is entered; 52 is a plurality of processors (M units) for performing signal processing of the input data; 53 is an output terminal through which the result of the processing by the processors 52 is output via an output bus; 70 is one frame of screen data to be output through the input terminal 51; and 71 is a plurality of divided windows constituting one frame of the screen data 70.

FIG. 7 is a block diagram showing a typical high efficiency coding algorithm. In this figure, reference numeral 51 is the input terminal; 60 is a motion compensation circuit that performs motion compensation on the input data from the input terminal 51; 61 is an interframe differentiation circuit that differentiates the data from the motion compensation circuit 60 and the data from the input terminal 51; 62 is a block discrimination circuit that separates the data from the interframe differentiation circuit 61 into significant and insignificant block; 63 is a codec circuit that codes and decodes the significant block data coming from the block discrimination circuit 62; 64 is an interframe addition circuit that adds the decoded data from the codec circuit 63 and the data from the motion compensation circuit 60; 65 is a coding frame memory that stores the data from the interframe addition circuit 64; 66 is a pre-processing circuit that includes the motion compensation circuit 60 and the interframe differentiation circuit 61; 67 is a post-processing circuit that contains the codec circuit 63 and the interframe addition circuit 64; and 68 is an output terminal through which the processed output data is output.

In operation, this video coding system addresses motion video signals as follows: The system divides one page of screen data 70 into M windows of screen data 71 which are assigned to the processors 52. It takes a single frame time for the processors 52 to get their respective window data 71. Then it takes another single frame time for the processors 52 to carry out the necessary process required of them. The results are synchronized between the processors 52 for output onto an output bus. At this time, the individually processed window data 71 are composed again into a single frame format.

When the processing method described above is employed, the time T required to turn one frame into M divisions for processing is given as ##EQU2## where,

T_(f) : time required for one processor to process one frame

T_(fn) : time required for an n-th processor to perform its processing per window

Therefore, increasing the number of data divisions allows processors 52 of a relatively low speed version to perform high speed video processing. Meanwhile, the slowest processor 52 determines the overall processing speed.

FIG. 7 thus illustrates the algorithm of a high-performance coder that addresses motion video screens. In this setup, the motion compensation circuit 60 performs motion compensation on all input data coming from the input terminal 51. After differentiation with the input data by the interframe differentiation circuit 61, only the significant blocks extracted by the block discrimination circuit 62 are sent to the codec circuit 63 for coding and decoding. At this point, the following relationship exists between the significant block ratio inside the windows α and the window processing time T: ##EQU3## where,

a, b: constants

B_(N) : number of blocks inside windows

FIG. 9 illustrates the relationship given by the expression (2) above. In the prior art video coding system, the processors 52 synchronize with one another in carrying out their input and output. That is, the same maximum processing time need to be assigned to each of the processors 52. As shown in FIG. 9, the system develops during operation an idle time which is represented by the area of the shaded portion.

In cases where it takes different times to perform the processing depending on the block to be processed, the prior art video coding system, structured as described above, requires assigning the longest processing time equally to each of its processors 52. This has lead to the problem of unnecessarily increasing the number of processors despite the redundancy in their performance.

FIG. 10 is a block diagram of a typical prior art digital signal processing system in its simplified form presented in "A DSP Architecture for 64 Kpbs Motion Video Codec" (International Symposium on Circuit and System, ISCAS '88, pp. 227-230, 1988). In FIG. 10, reference numeral 81 is an instruction memory that stores a microprogram instruction word; 82 is an instruction execution control circuit that reads an instruction word from the instruction memory 81, interprets it, and performs operational control accordingly; 83 is a data input bus that mainly transfers data and control signals; 84 is a data memory which stores operation data and which has a plurality of input/output ports; 85 is a data operation circuit that performs various operations on up to two pieces of input data coming from the data memory 84 via the data input bus 83; 86 is an address generation circuit that generates addresses independently for two pieces of data input to the data operation circuit 85 and one piece of data output therefrom; and 87 is a data output bus that transfers the results of the data operation.

The operations involved will now be described by referring to the flowchart in FIG. 11. This is an example in which two pieces of input data comprising "n" bits ("n" is an integer greater than 0) are subjected to a binary operation by the data operation circuit 85. The data (comprising "n" bits) resulting from the operation is subjected to a limiting process in which "m" bits ("m" is an integer equal to or greater than "n") are regarded as significant bits and handled as such.

The instruction execution control circuit 82 notifies the instruction memory 81 of the address given via an address path 101. The corresponding instruction word is read from the instruction memory 81 via a data path 102. The instruction execution control circuit 82 then interprets the instruction word that was read, provides the address generation circuit 86 with a control signal via a data path 104 and, as required, transmits data or the like onto the data input bus 83 via a data path 103.

The control signal causes the address generation circuit 86 to notify the data memory 84 of the addresses of the two pieces of input data ("n" bits each) needed for the operation involved. In turn, the data memory 84 sends the two pieces of input data onto the data input bus 83 via a data path 105. The data operation circuit 85 receives via a data path 106 the two pieces of input data placed on the data input bus 83. The data operation circuit 85 performs the binary operation specified by the instruction execution control circuit 82 by way of the data path 103. The resulting data (of "n" bits) is transmitted to the data output bus 87 via a data path 108. The data placed on the data output bus 87 is input via a data path 109 to the data memory 84, and is stored at the address therein given by the address generation circuit 96 via a data path 107. The above processes constitute step ST1.

In step ST2, following the above-described input operation, the data operation circuit 85 admits, again via the data path 106, the operation result data from the data memory 84. The data operation circuit 85 then executes a MAX instruction (whose significant bit count is "m"), one of the instruction sets specified by the instruction execution control circuit 82. The MAX instruction is an instruction which, when executed, takes the larger of the two maximum values: one represented by the operation result data and the other by the data of "m" significant bits, and handles the chosen value as the resulting output. A check is made to see if the operation result data exceeds the maximum value. If it does, a limiting process is carried out. The above-described output operation causes the data resulting from executing the MAX instruction to be stored into the data memory 84. This completes step ST2.

In step ST3, by performing the input operation described above, the data operation circuit 85 admits again via the data path 106 the data resulting from executing the MAX instruction, the data being retrieved from the data memory 84. Then a MIN instruction (whose significant bit count is "m"), one of the instruction sets, is executed. The MIN instruction is an instruction which, when executed, takes the smaller of the two minimum values: one represented by the operation result data and the other by the significant bit count "m" and handles the value as the resulting output. A check is made to see if the operation result data is smaller than the minimum value. If it is, a limiting process is carried out. The output operation described above causes the data resulting from executing the MIN instruction to be stored into the data memory 84. This completes step ST3.

The limiting process will now be described in more detail by referring to FIG. 12. In this example, operation result data of "n" bits (MSB and LSB denote the most and the least significant bit, respectively) is assumed, as shown in FIG. 12(a). In a limiting process involving "m" significant bits (m<n) , the high-order (n-m) bits are considered the data equivalent to the MSB. The remaining "m" bits are regarded as "m" bit data if the operation result data falls within a range represented by the "m" bits. If the operation result data exceeds the maximum value that can be represented by the "m" bits, the "m" bits are regarded unchanged as the "m" bit data; if the operation result data is smaller than the minimum value that can be represented by the "m" bits, the minimum value is regarded as the "m" bit data [FIG. 12(b)].

Where the significant bit count "m" equals "n", the limiting process is equivalent in effect to a case where no limiting process is carried out.

Since the prior art digital signal processing system is constructed as described above, performing the limiting process on operation result data has required executing as many as three instructions including an operation. This has led to the problem of reduced processing efficiency in prior art systems of this type.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a video codec system which averages the processing times of the DSP's configured, which connects to a receiving side of low resolution, and which reduces the capacity of receiving buffers.

It is another object of the present invention to provide a motion compensation method which simplifies and reduces in size the necessary hardware that reduces the amounts of operation involved without deteriorating its ability to detect the least distortion block.

It is a further object of the present invention to provide a video coding system which attains highly efficient processing using a minimum of processors.

It is an addition object of the present invention to provide a digital signal processing system capable of performing a highly efficient limiting process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the video coder embodying part of the prior art video codec system;

FIGS. 2(a) and 2(b) are views explaining the operation of dividing video data based on the prior art video codec method;

FIG. 3 is a functional block diagram depicting the construction of the prior art motion compensation interframe coding system;

FIGS. 4(a) and 4(b) are views illustrating the prior art motion vector detection method;

FIG. 5 is a view describing the prior art total search type motion vector detection method;

FIG. 6 is a view explaining the prior art tree search type motion vector detection method;

FIG. 7 is a block diagram showing a typical prior art high efficiency coding algorithm;

FIG. 8 is a block diagram depicting the prior art video coder;

FIG. 9 is a view explaining how the processing time shown in FIG. 8 is related to the rate of significant blocks;

FIG. 10 is a block diagram illustrating the construction of the prior art digital signal processing system;

FIG. 11 is a flowchart showing how the prior art digital signal processing system operates;

FIGS. 12(a) and 12(b) are views explaining the prior art limiting process;

FIG. 13 is a block diagram showing the construction of a video codec method as a first embodiment of the present invention;

FIGS. 14(a), 14(b), 14(c), 14(d) and 14(e) are views explaining a sub-sampling process according to the present invention;

FIG. 15 is a functional block diagram showing the construction of a motion compensation interframe coding system as a second embodiment of the present invention;

FIG. 16 is a functional block diagram indicating the internal construction of a motion compensation circuit according to the present invention;

FIG. 17 is a flowchart describing how the system according to the present invention works;

FIG. 18 is a view depicting how a mean value pattern is calculated;

FIG. 19 is a view explaining how motion vector detection is carried out by use of the mean value pattern in the first stage of search;

FIG. 20 is a view illustrating the deployment of search motion vectors during motion vector detection by use of a mean value pattern;

FIG. 21 is a view describing how motion vector detection is carried out in the second stage of search within the range defined by motion vector detection in the first stage of search;

FIG. 22 is a block diagram of a vector coding system as a third embodiment of the present invention;

FIG. 23 is a view depicting the relationship between the processing time and the significant block ratio for the third embodiment;

FIG. 24 is a block diagram showing the construction of a digital signal processing system as a fourth embodiment of the present invention; and

FIG. 25 is a flowchart outlining how the digital signal processing system according to the invention works.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A first embodiment of the present invention will now be described by referring to the accompanying drawings. FIG. 13 is a block diagram showing how the video codec method according to the present invention is typically embodied. In FIG. 13, reference numeral 6 is video data to be input; 7 is a data control circuit that distributes the video data 6 to coding-dedicated memories 8; 8 is a group of coding-dedicated memories that store the sub-sampled video data 6; 9 is a collection of coding circuits that code the sub-sampled video data 6 stored in the coding-dedicated memories 8; 10 is a codec control circuit that selects all of or adaptively selects part of video data 12 coded by the coding circuits 9 for composition and another sub-sampling followed by consecutive transmission; 11 is a group of address and data buses over which the coding circuits 9 read the sub-sampled video data 6 from the memories; 12 is the video data coded by the coding circuits 9; 13 is a coding mode control signal indicating whether the resolution of the receiving side is of standard or of sub-sampling type (1/2 resolution, 1/4 resolution, etc.); and 14 is transmission data composed and again sub-sampled in accordance with the resolution of the receiving side.

FIG. 14 illustrates a sub-sampling process in which one frame of video data is subjected to a subtracting or thinning-out operation so that the pixels involved do not overlay with one another when divided into a plurality of pieces of data. In this example, one frame of image data shown in FIG. 14(a) is divided into four pieces of sub-sampled video data [FIGS. 14(b) through 14(e): 1/4 sub-sampling]. As indicated in FIG. 14(a), if one frame of video data pixels is turned into four divisions identified by symbols O, X, Δ and □, these groups constitute sub-sampled video data with 1/4 resolution [1/4 sub-samples, in subfigures (b) through (e)]. FIG. 14(b), for example, show a set of data obtained by subtracting the pixels X, Δ and □ (other than pixels O) from the image data of FIG. 14(a). This necessarily means that the amount of data, i.e., the number of pixels, is a quarter of the total thereof.

In operation, the data control circuit 7 consecutively admits the video data 6 in units of frames. The input data is distributed to the coding-dedicated memories 8. After being stored in the coding-dedicated memories 8, the video data 6 is read into the coding circuits 9 disposed in parallel. After coding by the coding circuits 9, the coded video data 12 is output to the codec control circuit 10. As specified by the coding mode control signal 13, all of the coded video data 12 is selected or a part thereof is adaptively selected, and is composed and again sub-sampled in accordance with the number of coding circuits that the receiving side possesses. A header is attached to the sub-sampled data before it is forwarded frame by frame as the transmission data 14.

It is now assumed that, as illustrated in FIG. 14, there are four pieces of the 1/4 sub-sampled video data [FIGS. 14(b) through FIG. 14(e)]. There exist four coding circuits 9 disposed in parallel. The four pieces of sub-sampled video data are coded by the coding circuits 9 for output to the codec control circuit 10. If the coding mode control signal 13 calls for a standard mode (i.e., the resolution is the same as that of the receiving side), all four pieces of coded video data 12 are composed; if the coding mode control signal 13 calls for a 1/4 sub-sample mode (i.e., the resolution of the receiving side is 1/4), any one of the four pieces of the coded video data 12 may be selected (but composition thereof is not needed); if the coding mode control signal 13 calls for a 1/2 sub-sampling mode (i.e., the resolution of the receiving side is 1/2), any two of the four pieces of the coded video data 12 are selected and composed.

In the embodiment described above, 1/4 sub-sampling of video data is performed. Equivalent effects are obtained by carrying out 1/2n (n=1, 2, 3, . . . ) sub-sampling.

FIG. 15 shows how the compensation interframe coding system is constructed as the second embodiment of the present invention. Ill FIG. 15, reference numeral 37 is a mean value calculation circuit which, for each reproduction frame, turns a motion compensation block measuring l1×l2 into equal parts of a predetermined size (mean value blocks) so as to find the mean pixel count 38 of each mean value block. Reference numeral 39 is a mean value frame memory that retains the mean value 38 of mean value blocks per frame.

FIG. 16 depicts the internal construction of the motion compensation circuit 25. In this figure, reference numeral 41 is a mean value calculation circuit that calculates the mean value 38 of each mean value block within the block to be coded. Reference numeral 43 is an input mean value memory that retains as a pattern each mean value of the mean value blocks within the current input block.

Reference numeral 44 is a mean value pattern matching circuit that calculates the amount of distortion between the mean value pattern of the input block and the mean value pattern in the mean value frame memory 39 so as to detect the least distortion block. Reference numeral 46 is a pixel pattern matching circuit that detects the position of the least distortion block by calculating the amount of intraframe distortion between the input block and the search range compatible block in the frame memory.

FIGS. 18 and 19 show how the motion vector detection method according to the invention works in the first stage of search by use of the least distortion of the mean value pattern. In FIGS. 18 and 19, reference numeral 40 is a range of search for a reproduction frame mean value pattern; 42 is a mean value pattern of the input block; and 47 is a mean value block.

The effects of the present invention will now be described. The input signal 21 is coded by the coder 29 and decoded by the decoder 31, both conventionally, to become decoded reproduction data 33 which is stored also conventionally into the frame memory 34. At the same time, the data 33 in one frame is turned into mean value blocks 47 measuring k1×k2 each. The mean value of pixels is obtained for each mean value block as shown in FIG. 15.

A case may be assumed in which the mean value block is of a size by which a motion compensation block measuring l1×l2 may be divided into equal parts. In that case, there exist J mean values [J=(l1×l2)/(k1×k2)] within the l1×l2 block. At this time, the mean pixel value aj (j=1 to J) within each mean value block is collectively handled as a single pattern A. That is, A={a1, a2, . . . aJ}.

Motion vector detection is then carried out as outlined by the flowchart in FIG. 17. In step S1, i.e., in the first stage of search, the least distortion block is searched for through the search motion vectors in accordance with the mean value block size (FIG. 20).

In step S2, the mean value pattern 42 is calculated beforehand for the input block 23 by the mean value calculation circuit 41. Between the input block mean value pattern and the mean value pattern of the preceding frame corresponding to the block in the motion vector position, the mean value pattern matching circuit 44 performs matching distortion calculation and least distortion block detection (FIG. 19).

The mean value distortion is given by the following expression: ##EQU4## It is assumed here that the input block mean value pattern A={a1, a2, . . . aJ} and that the reproduction frame mean value pattern Ay={ay1, ay2, . . . aJ}.

Given the above settings, if mean value pattern matching is utilized, it takes l1×l2 machine cycles to calculate the mean value for each input block and reproduction frame block, and it takes J machine cycles to carry out each pass of mean value pattern matching.

Thus in the first stage of search, the required amount of operation C1 is given as

    C1=(l1×l2)×(M1+1)+M1×J×a+M1×b(108)

Here, M1 stands for the number of motion vectors in the first stage of search.

Step S3 is a motion detection step to be performed by the pixel pattern matching circuit 46. As shown in FIG. 21, a delimited search range 49 measuring m1×n1 is set around the least distortion block obtained by the mean value pattern matching circuit 44. Within this range, motion vectors to be searched for are disposed at a high concentration.

The amount of operation C2 within the delimited search range 49 is given as the sum of the following:

    {(2m1+1)(2n1+1)×L×a}                           (109)

    and

    (2m1+1)(2n1+1)+b                                           (compare operation)

where, l1=8; l2=8; m=8; n=8; k1=4, k2=4 for a mean value block; and operation machine cycle counts a=1 (absolute differential value) and b=2 (compare operation). Given these settings, the number of vectors to be searched for (M1) is 25, while J=4.

Therefore, the required amount of operation C1 in the first stage of search is about 1800 machine cycles.

In the second stage of search, where the search range is delimited by m1=3, n1=3, the required amount of operation C2 is about 3200 machine cycles.

As indicated above, the amount of operation per input block is 5000 machine cycles. This is about one fourth of the amount of operation conventionally required for total search.

The above-described embodiment illustratively involves dividing the current input block into small blocks and using a mean value pattern based on the mean value of pixels as a sample data pattern in each small block. However, the present invention is not limited to this embodiment; it can also be embodied so as to provide the same effects when using a sample data pattern that represents the value of pixels in specific positions within the small block.

A third embodiment of the present invention will now be described by referring to the accompanying drawings. In FIG. 22, reference numerals 51 and 53 are the input and the output terminal, respectively, mentioned earlier; 54 is an input frame memory that stores input data admitted through the input terminal 51; and 55 is a pre-stage multiprocessor which, connected to the input frame memory 54, comprises a plurality of processors 52 that may be expanded in parallel depending on the amount of processing to be performed. The pre-stage multiprocessor 55 codes all pixels of the data that is input from the input terminal 51. The multiprocessor 55 is also capable of adding significant/insignificant block information and intraframe position information to block data. Reference numeral 56 is a post-stage multiprocessor comprising a plurality of processors 52 that may also be expanded in parallel depending on the amount of processing to be performed. The post-stage multiprocessor 56 codes only significant blocks in the data that is input from the input terminal 51. The multiprocessor 56 is also capable of identifying significant blocks and re-composing frames based on the significant/insignificant block information and position information added by the pre-stage multiprocessor 55 to the block data.

Reference numeral 57 is a buffer disposed between the pre-stage multiprocessor 55 and the post-stage multiprocessor 56. The buffer 57 stores the coded data output by the pre-stage multiprocessor 55 and absorbs the difference in processing time between the two multiprocessors 55 and 56. Reference numeral 58 is an output control circuit which is connected to the post-stage multiprocessor 56 and receives the coded data therefrom. By sending feedback data to the pre-stage multiprocessor 55, the output control circuit 58 adjusts the threshold value for control over the amount of data to be coded. In this manner, the amount of coded data generated by the pre-stage multiprocessor 55 is held constant. At the same time, the output control circuit 58 varies the number of significant blocks depending on the quantity of data accumulated in the buffer 57, keeps constant the output of the post-stage multiprocessor 56, and transmits output data via the output terminal 53. Reference numeral 59 is a coding frame memory which, connected to the post-stage multiprocessor 56, stores the decoded data coming therefrom and sends it to the pre-stage multiprocessor 55 during the next frame processing.

Reference numeral 71 is block data which, having been processed by the pre-stage multiprocessor 55, is placed in the buffer 57. Reference numeral 72 is a collection of parameters that are added to each piece of block data 71; they indicate the attributes thereof.

The operations involved will now be described. The coding process that applies to the present invention may be divided into two stages: a pre-stage process in effect before conditional pixel compensation is performed, and a post-stage process that follows the pre-stage process. In that case, the expressions below indicate the relationship between the ratio of significant blocks α for the pre-stage or post-stage process and the processing time T:

    T=C (for pre-stage process)                                (3)

where, C is a constant;

    T=As (for post-stage process)                              (4)

where, A is a constant.

FIG. 23 illustrates what the above expressions (3) and (4) represent. As indicated, the coding process is composed of the pre-stage process and the post-stage process. The pre-stage process is a process in which the processing time remains constant regardless of the significant block ratio α. In the post-stage process, the processing time is proportional to the significant block ratio α. The pre-stage and the post-stage process are carried out respectively by the pre-stage multiprocessor 55 and the post-stage multiprocessor 56. Each multiprocessor is capable of being expanded in parallel depending on the amount of processing to be performed.

Input data is entered through the input terminal 51 into the input frame memory 54. The input data is then subjected to the pre-stage process in which motion compensation, conditional pixel compensation, etc. are carried out. The result is output to the buffer 57. The processors 57 that make up the pre-stage multiprocessor 55 admit block data from the input frame memory 54 in the order in which the data was processed. Because the processing time varies for each of the processors 52 depending on the block data, the order in which the data is output to the buffer 57 is not the same as the order in which the input frame memory 54 is scanned. Thus the data that is output to the buffer 57 from the processors 52 is given the position information indicating its intraframe position plus the significant/insignificant block information and data type information.

The block data placed in the buffer 57 is subjected to the post-stage process including vector quantization, discrete COS transformation and decoding. The coded data is output to the output control circuit 58 and the decoded data to the coding frame memory 59. At this point, the information added to the data is referenced and only the significant blocks are processed accordingly. The decoded data placed in the coding frame memory 59 is sent to the pre-stage multiprocessor 55 for coding of the next frame. The output control circuit 58 transmits feedback data to the pre-stage multiprocessor 55 for control over the threshold value in the pre-stage process. This keeps the amount of coded data constant. Furthermore, the output control circuit 58 monitors the quantity of data placed in the buffer 57 and, depending on the detected quantity of accumulated data, varies the number of significant blocks. This keeps the amount of processing constant in the post-stage process, thereby reducing the work load of the post-stage multiprocessor 56.

As shown in FIG. 23, there is a difference between the pre-stage processing time T₁ and the post-stage processing time T₂. This processing time difference (T₂ -T₁) is absorbed by the buffer 57 placed between the pre-stage multiprocessor 55 and the post-stage multiprocessor 56. This arrangement provides the processing performance closely approximating the maximum processing capacity of the pre-stage multiprocessor 55 or of the post-stage multiprocessor 56. As a result, the idle time indicated in FIG. 9 by broken line as an area is eliminated.

A fourth embodiment of the present invention will now be described by referring to the accompanying drawings. FIG. 24 is a block diagram depicting the construction of the digital signal processing system as the fourth embodiment of the invention. It is to be understood that like or corresponding parts in the fourth embodiment and the prior art digital signal processing system in FIG. 10 are given like reference characters, and that the description of these parts is omitted.

In FIG. 24, reference numeral 88 is a limiting circuit that directly admits the operation result data coming from the data operation circuit 85 via the data path 108. The limiting circuit 88 then limits the data to the number of significant bits designated by the instruction execution control circuit 82 via a data path 110.

The operations involved will now be described by referring to the flowchart in FIG. 25. There may be assumed a case in which two pieces of input data comprising "n" bits, n being an integer greater than zero, are subjected to a binary operation performed by the data operation circuit 85. The data resulting from the operation (comprising "n" bits) is subjected to a limiting process whereby the "m" bits, m being an integer equal to or smaller than "n" are made to constitute the significant bit count. The case above will now be described.

The instruction execution control circuit 82 notifies the instruction memory 81 of the address designated via the address path 101. After interpreting the corresponding instruction word, the instruction execution control circuit 82 sends a control signal over the data path 104 to the address generation circuit 86. At the same time, the circuit 82 transmits data or the like over the data path 103 onto the data input bus 83, and informs the limiting circuit 88 of the significant bit count via the data path 110.

The control signal causes the address generation circuit 86 to notify the data memory 84 of the addresses of the two pieces of input data ("n" bits each) to be operated on. In turn, the data memory 84 sends the two pieces of input data over the data path 105 onto the data input bus 83. The data operation circuit 85 admits, via the data path 106, the two pieces of input data from the data input bus 83. At this point, in step ST4, the circuit 85 performs on the data the binary operation which is designated by the instruction execution control circuit 82 via the data path 103. The operation result data ("n" bits) is output directly to the limiting circuit 88 over the data path 108. The limiting circuit 88, in step ST5, limits the operation result data to the significant bit count "m" designated by the instruction execution control circuit 82 via the data path 110. The limited operation result data is placed onto the data output bus 87 via a data path 111. This operation result packet sent over the data output bus 87 is input to the data memory 84 via the data path 109. The packet is stored at the address given again by the address generation circuit 86 via the data path 107. This completes step ST5. In the steps described above, one instruction allows both the operation and the limiting process to be performed.

As described, according to the present invention, sub-sampled video data is input consecutively in units of frames. The data is coded in parallel by coding circuits. All of the coded video data is selected or a part thereof is adaptively selected for composition in accordance with the resolution of the receiving side. Upon transmission, the data is sub-sampled again depending on the number of coding circuits that the receiving side possesses. The sub-sampled parts of the data are consecutively given headers when transmitted. This arrangement substantially averages the numbers of significant pixels among the coding circuits and minimizes the overall processing time accordingly. Furthermore, it is possible to establish connection with a receiving side with low resolution and to eliminate the conventionally experienced time difference in reception and coding. This makes it possible to reduce the receiving buffer capacity.

Also according to the present invention, the amount of pattern-to-pattern distortion for the intrablock mean value may be used to localize the range in which to search for motion vectors. This prevents matching errors during the localizing. Because highly concentrated motion vector search is carried out within the localized area, the amount of operation is reduced and the necessary hardware is simplified accordingly. This in turn constitutes a motion compensation method capable of detection motion vectors with high precision.

Further according to the present invention, a pre-stage multiprocessor and a post-stage multiprocessor are provided to separately perform two processes: coding all pixels, and coding only significant blocks. With a threshold value controlled, the amount of coded data from the pre-stage multiprocessor is kept constant accordingly. A buffer is provided to absorb operational differences between the two multiprocessors. Depending on the amount of data accumulated in the buffer, the number of significant blocks is varied so as to keep constant the output of the post-stage multiprocessor. This arrangement eliminates the need to set the processing time for the least favorable value. Because each of the processors configured is always tapped to capacity in performance, the number thereof required for the necessary processing may be reduced.

Still according to the present invention, operation result data that is output by a data operation circuit is directly input to a limiting circuit. The limiting circuit then limits the data to a suitable significant bit count designated by an instruction execution control circuit. This arrangement allows a single instruction to perform both the operation and the limiting process. This provides for a digital signal processing system capable of an efficient limiting process. 

What is claimed is:
 1. A digital signal processing system, comprising:an instruction memory for storing microinstructions; an instruction execution control circuit for fetching and decoding said microinstructions from said instruction memory, each of said microinstructions including a data operation instruction and a bit limiting instruction designating a significant bit count; a data memory for storing data; a data operation circuit for performing an operation on data from said data memory, said operation being designated by a decoded microinstruction from said instruction execution control circuit; and a limiting circuit for inputting a result of said operation performed by said data operation circuit, inputting a bit limiting instruction from said instruction execution control unit, physically limiting the number of bits of said result to any integer m designated by the bit limiting instruction of said decoded microinstruction, and outputting the limited result to an output bus with a width of n bits, where m<n. 